The present invention relates to semiconductor memory devices and more particularly, to a row redundancy circuit suitable for high density memory devices and semiconductor memory devices having the same.
It is well known that the redundancy circuit increases the yield of the semiconductor memory devices. The redundancy circuit replaces a defective memory cell with a spare or redundant memory cell. A row redundancy circuit, for example, decodes the row address for designating the defective memory cell to replace the defective memory cell with a spare memory cell. Here, the "row" extends along the direction of the word lines. In general, the higher density a semiconductor memory device has, the more memory cells the semiconductor memory device includes in the unit area. Further, a memory cell array is divided into a number of memory cell array blocks, and the memory cell array blocks increase in number as the density of the semiconductor memory device increases.
FIG. 1 is a schematic diagram of a conventional redundancy circuit. In the drawing, a memory cell array is divided into four memory cell array blocks MA0, MA1, MA2 and MA3. Each of the memory cell array blocks MA0, MA1, MA2 and MA3 includes normal row decoders X0, X1, X2 and X3 and spare word lines (SW00-SW03; SW10-SW13; SW20-SW23; and SW30-SW33). Spare row decoders SD0, SD1, SD2 and SD3 are then provided for driving the spare word lines during the redundancy operation. The number of the spare row decoders SD0, SD1, SD2 and SD3 is the same as the number of the spare word lines in each of memory cell array block MA0, MA1, MA2 and MA3. The spare row decoders SD0, SD1, SD2 and SD3 receive the address signals A0.about.An-3, to drive the spare word lines. Thus, when a defect occurs at a normal word line in, for example, the memory cell array block MA0, the defect is programmed in the spare row decoders SD0, SD1, SD2 and SD3 to replace the defective normal word line with the spare word lines SW00-SW03. In this device, however, although one or two normal word lines are defective in the same memory cell array block, four spare word lines in the same redundant memory cell array are all substituted for the defective normal word lines including non-defective word lines, thus reducing the efficiency of the redundancy. Further, since the respective memory cell array blocks include their own four spare word lines, the chip size will increase.
In FIG. 2, another conventional redundancy circuit is shown which can solve the above-mentioned problems. This device includes the memory cell array blocks MA0-MA3 each having two spare word lines which are fewer in number than that of FIG. 1, and spare row decoders SD0-SD7 each for driving the respective spare word lines SW00, SW01, SW10, SW11, SW20, SW21, SW30 and SW31. Accordingly, if a normal word line is defective, only the defective word line is replaced with a spare word line, under the control of the corresponding spare row decoder. Such a redundancy circuit can substitute the defective word lines on a line-by-line basis, because the spare word lines SW00, SW01, SW10, SW11, SW20, SW21, SW30 and SW31 are controlled by their own spare row decoders SD0-SD7. However, when more than two normal word lines are defective, the defect cannot be repaired, because each memory cell array block includes only two spare word lines. Further, it is not possible to repair a defective normal word line in a memory cell array block by using a spare word line in an adjacent memory cell array block. More significantly, since each spare word line should be connected to its own spare row decoder, the total number of the spare decoders increases, which would inevitably be reduced in a high density memory device.
FIG. 3 shows another conventional redundancy circuit for solving the problems mentioned above, which is disclosed in Korean patent application 12437/1992 filed by Samsung Electronics. The conventional device includes a memory cell array divided into four memory cell array blocks 10A, 10B, 10C and 10D. Of the four memory cell array blocks, the memory cell array block 10B only includes a redundant memory cell array consisting of spare word lines SW0-SW3. Further, a number of fuse boxes 1 through 4 are provided to repair any defective word lines from the memory cell array blocks 10A, 10B, 10C and 10D, by using the spare word lines SW0-SW3. However, since the spare word lines are all concentrated in the memory cell array block 10B, the capacitances formed between bit lines of the memory cell array block 10B become higher, compared to other memory cell array blocks 10A, 10C and 10D, thus causing relatively lower sensing ability. Moreover, the output signals RED0-RED3 from the fuse boxes 1 to 4 are supplied to a spare word line driver and redundant block control signal generator 5 by way of bus lines interposed therebetween. In the high density semiconductor memory devices, if the bus lines are arranged in the core portion of the memory devices, it would be disadvantageous for the effective lay-out and the high density of the chips.